This invention relates to a dynamic random-access memory (DRAM) that operates in synchronization with a clock signal, thus being suitable for integration into microcontrollers and application-specific integrated circuits.
A microcontroller, for example, generally comprises a central processing unit, read-only memory, random-access memory, and other modules integrated onto a single semiconductor chip. Operations of all on-chip circuits are synchronized by a system clock signal. In the past, the random-access memory has generally been of the static type (SRAM), which has a simple control scheme permitting rapid access and can easily be synchronized to the system clock. For many purposes it would be desirable to use DRAM, Which takes up less space and dissipates less power than SRAM, but the more complex control required by DRAM has been an obstacle.
In prior-art DRAM, the timing of address input and data output is determined by a plurality of control signals. Even if these control signals are generated by the central processing unit in synchronization with the system clock, because of unavoidable fabrication variations in circuit elements, synchronization between the system clock and DRAM input and output operations will be inaccurate. Inaccurate synchronization must be allowed for by employing a low clock frequency, which of course limits the speed of the entire device.